Changelog
Stay up to date with the latest features, performance improvements, and bug fixes for DigiSim.
v2.5.0 Latest
March 2026
v2.5.0 Latest
March 2026
Added subscription-based pricing with monthly and yearly plans
New billing toggle on pricing page
Improved landing page performance with lazy-loaded sections
Enhanced SEO with structured data on all public pages
v2.4.0
February 2026
v2.4.0
February 2026
SimCast interactive lesson player improvements
New component documentation with live examples
Cloud circuit storage optimization
Bug fixes for oscilloscope waveform rendering
v2.3.0
January 2026
v2.3.0
January 2026
Added 70+ pre-built circuit templates across 7 categories
New featured circuits showcase on landing page
SEO-friendly template circuit URLs with slugs
Performance improvements for large circuits
v2.2.0
December 2025
v2.2.0
December 2025
Introduced DigiSim Pro subscription tier
Added 8-channel oscilloscope for advanced timing analysis
Assembly Program Loader for CPU projects
Cloud save with automatic synchronization
v2.1.0
December 2025
v2.1.0
December 2025
Added the 8-Bit ALU (Arithmetic Logic Unit) as a core component, supporting addition, subtraction, AND, and OR operations.
Significantly improved simulation performance for large circuits with over 100 components.
Resolved an issue where wire connections would sometimes misalign after dragging a component.
v2.0.0
June 2025
v2.0.0
June 2025
Introduced custom components (sub-circuits) for Pro users. You can now encapsulate a circuit and reuse it as a single block in other designs.
Launched our new documentation pages to better support our users.
Redesigned the main component toolbar for a cleaner look and more intuitive grouping of components.
Fixed a bug that caused the Clock component to occasionally skip a pulse at high frequencies.
v1.5.0
May 2025
v1.5.0
May 2025
Added the 8-bit Register and Tri-State Buffer components, essential for building computer memory systems.
Users can now add labels to any component to better document their circuits.
Corrected the output behavior of the XNOR gate which was inverted in some cases.
v1.4.0
April 2025
v1.4.0
April 2025
Introduced the 4-bit Adder component for arithmetic operations in digital circuits.
Enhanced the wire routing algorithm to prevent overlapping connections.
Fixed simulation freezing issues when using multiple clock sources.
v1.3.0
March 2025
v1.3.0
March 2025
Added support for multi-bit buses to handle complex data paths.
Improved the user interface with better component icons and tooltip descriptions.
Resolved memory leaks that occurred during long simulation sessions.
Initial Release • Jan 2024